Data content scrubbing approach for SRAM based FPGA designs

  • J. Gomez-Cornejo
  • , I. Villalta
  • , I. Aranzabal
  • , I. Lopez
  • , A. Zuloaga

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)

Abstract

The configuration memory of SRAM-based FPGAs can be susceptible to induced faults potentially causing errors that may impact devices' functionality (depending on the criticality of the affected bit). The accumulation of those errors increase the probability of malfunction. The scrubbing is a hardening technique utilized to refresh the configuration memory of the FPGA, which defines the functionality of the device and can store user data content. While, scrubbing of the configuration memory of FPGAs is a well established strategy, the scrubbing of the data content has not been sufficiently addressed. Due to this, the present work proposes a scrubbing approach to clean errors from the data memories implemented as BRAMs or distributed memories based, and physically validated, on the ZYNQ from Xilinx.

Original languageEnglish
Title of host publication2022 IEEE 31st International Symposium on Industrial Electronics, ISIE 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages649-654
Number of pages6
ISBN (Electronic)9781665482400
DOIs
Publication statusPublished - 2022
Externally publishedYes
Event31st IEEE International Symposium on Industrial Electronics, ISIE 2022 - Anchorage, United States
Duration: 1 Jun 20223 Jun 2022

Publication series

NameIEEE International Symposium on Industrial Electronics
Volume2022-June

Conference

Conference31st IEEE International Symposium on Industrial Electronics, ISIE 2022
Country/TerritoryUnited States
CityAnchorage
Period1/06/223/06/22

Keywords

  • FPGA
  • bitstream
  • fault
  • memory
  • scrubbing

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