Fast and accurate single bit error injection into SRAM Based FPGAs

U. Kretzschmar; A. Astarloa; J. Jiménez; M. Garay; J. De Ser

doi:10.1109/FPL.2012.6339175

Fast and accurate single bit error injection into SRAM Based FPGAs

U. Kretzschmar, A. Astarloa, J. Jiménez, M. Garay, J. De Ser

Artificial Intelligence

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Abstract

The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.

Original language	English
Title of host publication	Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Pages	675-678
Number of pages	4
DOIs	https://doi.org/10.1109/FPL.2012.6339175
Publication status	Published - 2012
Event	22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway Duration: 29 Aug 2012 → 31 Aug 2012

Publication series

Name	Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Conference

Conference	22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Country/Territory	Norway
City	Oslo
Period	29/08/12 → 31/08/12

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10.1109/FPL.2012.6339175

Cite this

Kretzschmar, U., Astarloa, A., Jiménez, J., Garay, M., & De Ser, J. (2012). Fast and accurate single bit error injection into SRAM Based FPGAs. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012 (pp. 675-678). Article 6339175 (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012). https://doi.org/10.1109/FPL.2012.6339175

@inproceedings{b41635616cae4b81b2faabaf9618c72f,

title = "Fast and accurate single bit error injection into SRAM Based FPGAs",

abstract = "The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.",

author = "U. Kretzschmar and A. Astarloa and J. Jim{\'e}nez and M. Garay and {De Ser}, J.",

year = "2012",

doi = "10.1109/FPL.2012.6339175",

language = "English",

isbn = "9781467322560",

series = "Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012",

pages = "675--678",

booktitle = "Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012",

note = "22nd International Conference on Field Programmable Logic and Applications, FPL 2012 ; Conference date: 29-08-2012 Through 31-08-2012",

}

Kretzschmar, U, Astarloa, A, Jiménez, J, Garay, M & De Ser, J 2012, Fast and accurate single bit error injection into SRAM Based FPGAs. in Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012., 6339175, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, pp. 675-678, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 29/08/12. https://doi.org/10.1109/FPL.2012.6339175

Fast and accurate single bit error injection into SRAM Based FPGAs. / Kretzschmar, U.; Astarloa, A.; Jiménez, J. et al.
Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 675-678 6339175 (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.

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Kretzschmar U, Astarloa A, Jiménez J, Garay M, De Ser J. Fast and accurate single bit error injection into SRAM Based FPGAs. In Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. 2012. p. 675-678. 6339175. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012). doi: 10.1109/FPL.2012.6339175

Fast and accurate single bit error injection into SRAM Based FPGAs

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