Abstract
A fixed-throughput vector precoding (VP) approach specially suitable for hardware implementation in field programmable gate array (FPGA) devices is presented in this paper. The algorithm, which is based on the sphere encoder (SE), is divided into two main stages: at the preprocessing stage, the columns of the precoding matrix are ordered following any of the ordering approaches that have been proposed in this paper. Secondly, the search tree is configured so as to yield an appropriate bit error rate (BER) performance. Simulation results show that the BER performance of the proposed algorithm is very close to that of the SE, whereas its complexity is significantly smaller.
Original language | English |
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Pages (from-to) | 2406-2410 |
Number of pages | 5 |
Journal | European Signal Processing Conference |
Publication status | Published - 2009 |
Event | 17th European Signal Processing Conference, EUSIPCO 2009 - Glasgow, United Kingdom Duration: 24 Aug 2009 → 28 Aug 2009 |