TY - JOUR
T1 - Minimum signal modulation scheme based on a single carrier for interleaved operation of parallel phase legs in voltage source converters
AU - Capella, Gabriel J.
AU - Gabiola, Igor
AU - Pou, Josep
AU - Zaragoza, Jordi
AU - Ceballos, Salvador
AU - Agelidis, Vassilios G.
PY - 2014
Y1 - 2014
N2 - Connecting legs in parallel is a common way to increase the output current of a power converter. Interleaving the carriers used to modulate the reference signals for each leg leads to a reduction in the output current ripple without resorting to increasing the switching frequency. A whole set of shifted carriers is required if interleaved pulse-width modulators (PWMs) are used. Implementing this by means of a digital signal processor (DSP) means that the higher the number of carriers, the higher the number of DSP timing resources required. Provided that the latter are usually limited, this could be a drawback when increasing the number of interleaved carriers. This study presents the implementation of a PWM scheme where all modulators use the same carrier offering the same results as if a set of n interleaved carriers were used. Since the proposed algorithm takes maximum benefit from the PWM units available in a DSP, a higher number of legs connected in parallel can be controlled without adding any external processing hardware. A MATLAB/Simulink model has been set up for simulation purposes. Selected experimental results obtained from a three-leg single-phase inverter are reported, confirming the effectiveness of the proposed implementation.
AB - Connecting legs in parallel is a common way to increase the output current of a power converter. Interleaving the carriers used to modulate the reference signals for each leg leads to a reduction in the output current ripple without resorting to increasing the switching frequency. A whole set of shifted carriers is required if interleaved pulse-width modulators (PWMs) are used. Implementing this by means of a digital signal processor (DSP) means that the higher the number of carriers, the higher the number of DSP timing resources required. Provided that the latter are usually limited, this could be a drawback when increasing the number of interleaved carriers. This study presents the implementation of a PWM scheme where all modulators use the same carrier offering the same results as if a set of n interleaved carriers were used. Since the proposed algorithm takes maximum benefit from the PWM units available in a DSP, a higher number of legs connected in parallel can be controlled without adding any external processing hardware. A MATLAB/Simulink model has been set up for simulation purposes. Selected experimental results obtained from a three-leg single-phase inverter are reported, confirming the effectiveness of the proposed implementation.
UR - http://www.scopus.com/inward/record.url?scp=84899627642&partnerID=8YFLogxK
U2 - 10.1049/iet-pel.2013.0545
DO - 10.1049/iet-pel.2013.0545
M3 - Article
AN - SCOPUS:84899627642
SN - 1755-4535
VL - 7
SP - 1305
EP - 1312
JO - IET Power Electronics
JF - IET Power Electronics
IS - 5
ER -