Analysis of voltage balancing limits in modular multilevel converters

Salvador Ceballos; Josep Pou; Sanghun Choi; Maryam Saeedifard; Vassilios Agelidis

doi:10.1109/IECON.2011.6120032

Analysis of voltage balancing limits in modular multilevel converters

Salvador Ceballos^*
, Josep Pou
, Sanghun Choi
, Maryam Saeedifard
, Vassilios Agelidis

^*Autor correspondiente de este trabajo

Digitalización de equipos para la red eléctrica

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

51 Citas (Scopus)

Resumen

The modular multilevel converter (MMC) is one of the most promising converter topologies for high-voltage applications, especially for high-voltage direct-current (HVDC) transmission systems. One of the most challenging issues associated with the MMC is the capacitor voltage variations, which if not properly controlled, result in large circulating currents flowing through the converter legs. This paper develops a mathematical model to formulate and analyze capacitor voltage variations and the circulating currents within the MMC legs. Based on the developed model, the limits to the capacitor voltage balancing task are derived and graphically presented. A set of simulation results conducted in MATLAB/Simulink environment are presented to verify the accuracy of the mathematical analysis.

Idioma original	Inglés
Título de la publicación alojada	Proceedings
Subtítulo de la publicación alojada	IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society
Páginas	4397-4402
Número de páginas	6
DOI	https://doi.org/10.1109/IECON.2011.6120032
Estado	Publicada - 2011
Evento	37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 - Melbourne, VIC, Australia Duración: 7 nov 2011 → 10 nov 2011

Serie de la publicación

Nombre	IECON Proceedings (Industrial Electronics Conference)

Conferencia

Conferencia	37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011
País/Territorio	Australia
Ciudad	Melbourne, VIC
Período	7/11/11 → 10/11/11

ODS de las Naciones Unidas

Este resultado contribuye a los siguientes Objetivos de Desarrollo Sostenible

ODS 7: Energía asequible y no contaminante

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Ceballos, S., Pou, J., Choi, S., Saeedifard, M., & Agelidis, V. (2011). Analysis of voltage balancing limits in modular multilevel converters. En Proceedings: IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society (pp. 4397-4402). Artículo 6120032 (IECON Proceedings (Industrial Electronics Conference)). https://doi.org/10.1109/IECON.2011.6120032

@inproceedings{bbfa567728914958ba81a824f33b21b2,

title = "Analysis of voltage balancing limits in modular multilevel converters",

abstract = "The modular multilevel converter (MMC) is one of the most promising converter topologies for high-voltage applications, especially for high-voltage direct-current (HVDC) transmission systems. One of the most challenging issues associated with the MMC is the capacitor voltage variations, which if not properly controlled, result in large circulating currents flowing through the converter legs. This paper develops a mathematical model to formulate and analyze capacitor voltage variations and the circulating currents within the MMC legs. Based on the developed model, the limits to the capacitor voltage balancing task are derived and graphically presented. A set of simulation results conducted in MATLAB/Simulink environment are presented to verify the accuracy of the mathematical analysis.",

author = "Salvador Ceballos and Josep Pou and Sanghun Choi and Maryam Saeedifard and Vassilios Agelidis",

year = "2011",

doi = "10.1109/IECON.2011.6120032",

language = "English",

isbn = "9781612849720",

series = "IECON Proceedings (Industrial Electronics Conference)",

pages = "4397--4402",

booktitle = "Proceedings",

note = "37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011 ; Conference date: 07-11-2011 Through 10-11-2011",

}

Ceballos, S, Pou, J, Choi, S, Saeedifard, M & Agelidis, V 2011, Analysis of voltage balancing limits in modular multilevel converters. En Proceedings: IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society., 6120032, IECON Proceedings (Industrial Electronics Conference), pp. 4397-4402, 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011, Melbourne, VIC, Australia, 7/11/11. https://doi.org/10.1109/IECON.2011.6120032

Analysis of voltage balancing limits in modular multilevel converters. / Ceballos, Salvador; Pou, Josep; Choi, Sanghun et al.
Proceedings: IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society. 2011. p. 4397-4402 6120032 (IECON Proceedings (Industrial Electronics Conference)).

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - Analysis of voltage balancing limits in modular multilevel converters

AU - Ceballos, Salvador

AU - Pou, Josep

AU - Choi, Sanghun

AU - Saeedifard, Maryam

AU - Agelidis, Vassilios

PY - 2011

Y1 - 2011

N2 - The modular multilevel converter (MMC) is one of the most promising converter topologies for high-voltage applications, especially for high-voltage direct-current (HVDC) transmission systems. One of the most challenging issues associated with the MMC is the capacitor voltage variations, which if not properly controlled, result in large circulating currents flowing through the converter legs. This paper develops a mathematical model to formulate and analyze capacitor voltage variations and the circulating currents within the MMC legs. Based on the developed model, the limits to the capacitor voltage balancing task are derived and graphically presented. A set of simulation results conducted in MATLAB/Simulink environment are presented to verify the accuracy of the mathematical analysis.

AB - The modular multilevel converter (MMC) is one of the most promising converter topologies for high-voltage applications, especially for high-voltage direct-current (HVDC) transmission systems. One of the most challenging issues associated with the MMC is the capacitor voltage variations, which if not properly controlled, result in large circulating currents flowing through the converter legs. This paper develops a mathematical model to formulate and analyze capacitor voltage variations and the circulating currents within the MMC legs. Based on the developed model, the limits to the capacitor voltage balancing task are derived and graphically presented. A set of simulation results conducted in MATLAB/Simulink environment are presented to verify the accuracy of the mathematical analysis.

UR - https://www.scopus.com/pages/publications/84863036357

U2 - 10.1109/IECON.2011.6120032

DO - 10.1109/IECON.2011.6120032

M3 - Conference contribution

AN - SCOPUS:84863036357

SN - 9781612849720

T3 - IECON Proceedings (Industrial Electronics Conference)

SP - 4397

EP - 4402

BT - Proceedings

T2 - 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011

Y2 - 7 November 2011 through 10 November 2011

ER -

Analysis of voltage balancing limits in modular multilevel converters

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