Design, simulation and hardware validation of a low-cost CLMS echo canceling system

Pablo Prieto*, Mikel Sanchez, Javier Del Ser, Mikel Mendicute

*Autor correspondiente de este trabajo

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

4 Citas (Scopus)

Resumen

This paper presents the design, simulation and performance of a low-cost echo canceler for its application to on-channel repeaters in single frequency DVB-T networks. In these devices an echo canceler is required in order to avoid the coupling echoes produced between transmission and reception antennas. The designed echo canceler is based on an adaptive FIR Alter where a correlation-based LMS algorithm (namely, CLMS) is used for updating the set of complex coefficients under a Minimum Squared Error (MSE) criteria. The implemented prototype includes an Analog Devices floating-point DSP and a Virtex II Pro FPGA core. Computer simulation results and the registered in-lab measurements of the prototype verify that our approach shows surprisingly satisfactory echo attenuation capabilities at a minimal computational cost.

Idioma originalInglés
Título de la publicación alojada2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
DOI
EstadoPublicada - 2009
Evento2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 - Toulouse, Francia
Duración: 28 jun 20091 jul 2009

Serie de la publicación

Nombre2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

Conferencia

Conferencia2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
País/TerritorioFrancia
CiudadToulouse
Período28/06/091/07/09

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