TY - GEN
T1 - Design, simulation and hardware validation of a low-cost CLMS echo canceling system
AU - Prieto, Pablo
AU - Sanchez, Mikel
AU - Ser, Javier Del
AU - Mendicute, Mikel
PY - 2009
Y1 - 2009
N2 - This paper presents the design, simulation and performance of a low-cost echo canceler for its application to on-channel repeaters in single frequency DVB-T networks. In these devices an echo canceler is required in order to avoid the coupling echoes produced between transmission and reception antennas. The designed echo canceler is based on an adaptive FIR Alter where a correlation-based LMS algorithm (namely, CLMS) is used for updating the set of complex coefficients under a Minimum Squared Error (MSE) criteria. The implemented prototype includes an Analog Devices floating-point DSP and a Virtex II Pro FPGA core. Computer simulation results and the registered in-lab measurements of the prototype verify that our approach shows surprisingly satisfactory echo attenuation capabilities at a minimal computational cost.
AB - This paper presents the design, simulation and performance of a low-cost echo canceler for its application to on-channel repeaters in single frequency DVB-T networks. In these devices an echo canceler is required in order to avoid the coupling echoes produced between transmission and reception antennas. The designed echo canceler is based on an adaptive FIR Alter where a correlation-based LMS algorithm (namely, CLMS) is used for updating the set of complex coefficients under a Minimum Squared Error (MSE) criteria. The implemented prototype includes an Analog Devices floating-point DSP and a Virtex II Pro FPGA core. Computer simulation results and the registered in-lab measurements of the prototype verify that our approach shows surprisingly satisfactory echo attenuation capabilities at a minimal computational cost.
UR - http://www.scopus.com/inward/record.url?scp=72249101710&partnerID=8YFLogxK
U2 - 10.1109/NEWCAS.2009.5290486
DO - 10.1109/NEWCAS.2009.5290486
M3 - Conference contribution
AN - SCOPUS:72249101710
SN - 9781424445738
T3 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
BT - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
T2 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
Y2 - 28 June 2009 through 1 July 2009
ER -