TY - GEN
T1 - Fast and accurate single bit error injection into SRAM Based FPGAs
AU - Kretzschmar, U.
AU - Astarloa, A.
AU - Jiménez, J.
AU - Garay, M.
AU - De Ser, J.
PY - 2012
Y1 - 2012
N2 - The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.
AB - The design process of safety-aware FPGA designs does not only require a robust architecture, but also an appropriate method of verifying correct system behaviour in presence of errors. One error type, Single Event Upsets (SEU), are rare events, so technologies of either external- or internal error injection are used to emulate this kind of error. While external injection typically has a slow emulation speed, internal injection is faster but also prone to so-called injection side effects. This work introduces a flow together with a mathematical framework, which allows the variable trade-off between emulation accuracy and emulation speed.
UR - https://www.scopus.com/pages/publications/84870699841
U2 - 10.1109/FPL.2012.6339175
DO - 10.1109/FPL.2012.6339175
M3 - Conference contribution
AN - SCOPUS:84870699841
SN - 9781467322560
T3 - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
SP - 675
EP - 678
BT - Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
T2 - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Y2 - 29 August 2012 through 31 August 2012
ER -